Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. One type of PLD, the field-programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) that are programmably interconnected to each other and to programmable input/output blocks (IOBs). This collection of configurable logic is personalized by loading configuration data into internal configuration memory cells that define how the CLBs, interconnections, and IOBs are configured. For a detailed discussion of an exemplary FPGA, see U.S. Pat. No. 6,144,220 entitled “FPGA Architecture Using Multiplexers that Incorporate a Logic Gate,” by Steven P. Young, which is incorporated herein by reference.
FIG. 1 (Prior Art) depicts a conventional FPGA 100, examples of which include the Spartan™ and Virtex™ FPGAs available from Xilinx, Inc., of San Jose, Calif. FPGA 100 includes an array of programmably interconnected CLBs 105. FPGA 100 additionally includes a clock distribution network 110 that can be connected to internal or external clock sources via a global clock buffer BUFG. Many other FPGA resources are omitted from FIG. 1 for brevity.
Manufacturers of PLDs, including FPGAs, would like to guarantee the highest speed performance possible without their devices failing to meet timing specifications. PLD designers therefore measure circuit timing as accurately as possible to minimize the guard bands required to ensure correct device performance. U.S. Pat. No. 6,144,262 entitled “Circuit for Measuring Signal Delays of Asynchronous Register Inputs,” by Christopher Kingsley describes circuits and methods of measuring circuit timing in programmable logic devices, and is incorporated herein by reference. U.S. Pat. No. 5,795,068 entitled “Method and Apparatus for Measuring Localized Temperatures and Voltages on Integrated Circuits,” by Robert O. Conn describes ring oscillator configurations on FPGAs, and is also incorporated herein by reference.
Clock distribution network 110 includes a source spine 110S that conveys clock signals to a source node 112 in the interior of FPGA 100. From there, a horizontal spine 110H conveys clock signals to a number of vertical clock spines 110V. Finally, a number of clock destination branches 110D extend to each CLB 105. Clock distribution network 110 can be programmably connected to any of CLBs 105 via programmable interconnect points. The above-cited Young patent describes exemplary programming technologies.
Clock distribution network 110 typically includes clock buffers 115 placed and sized to minimize clock skew, where skew is defined as the difference in path delays from clock input GCLK to each of CLBs 105 and any other clock loads, such as embedded blocks of memory and IOBs. Many different buffer and conductor configurations are possible, the selected implementation depending upon design requirements.
High-performance clock distribution networks, such as network 110, are designed to minimized clock skew. The delays inherent in network 110 are typically short relative to the delays associated with other FPGA resources. The short skew is beneficial from the standpoint of performance, but renders difficult the task of accurately determining clock skew because conventional test circuitry normally introduces more skew than the clock distribution network. There is therefore a need for a more accurate means of measuring skew on programmable logic devices.